Semiconductor integrated circuit

ABSTRACT

A semiconductor integrated circuit in which multiphase clock signals having the same phase difference are supplied from a multi-stage differential ring oscillator to other circuits, the multiphase clock signals can be prevented from being degraded in waveform due to electrostatic coupling between wirings of the multiphase clock signals and also wired in as small an area as possible. The semiconductor integrated circuit includes: multiple stages of amplifier circuits, connected in a ring form, for performing oscillating operation; a logic circuit for performing logic operation on the basis of predetermined ones of output signals of the multiple stages of amplifier circuits to output a plurality of clock signals having different phases from each other and duties not equal to 0.5; and a plurality of wirings for transmitting the plurality of clock signals output from the logic circuit.

TECHNICAL FIELD

[0001] The present invention relates generally to a semiconductorintegrated circuit and more particularly to a semiconductor integratedcircuit including a differential ring multiphase oscillator.

BACKGROUND ART

[0002] For signal transmission among devices, a technique employinghigh-speed and small-amplitude serial signals has been in use in recentyears. Compared with a technique that transmits digital signals inparallel, this technique needs only a small number of cables and alsocan minimize electromagnetic interference (EMI) caused by the digitalsignal transmission.

[0003] To realize a high-speed serial communication, a parallel-serialconverter is required on a transmit side which converter convertsparallel data into serial data by using sub-clock signals havingmultiple phases (hereinafter, such clock signals are referred to asmultiphase clock signals). The multiphase clock signals are synchronouswith a base clock signal and have the same phase difference. Further, amultiphase clock generator is required which generates the multiphaseclock signals and supplies them to the parallel-serial converter.

[0004] An example of the multiphase clock generator is avoltage-controlled or current-controlled differential ring oscillatorhaving multiple stages of delayed differential inverted amplifiersconnected in a ring form. By using such a ring oscillator, it ispossible to easily draw multiphase clock signals having the same phasedifference out of the multi-staged amplifiers. However, in the case ofdesigning wiring layout for the multiphase clock signals havingprecisely equal phase differences from the high-speed ring oscillator tothe parallel-serial converter, the influences of electrostatic couplingbetween different wirings must be made uniform.

[0005]FIG. 1 shows a voltage-controlled differential ring oscillatorused in conventional semiconductor integrated circuits. As shown in FIG.1, the voltage-controlled differential ring oscillator 100 includes Nstages of delayed differential inverted amplifiers 101 a-101 j whichperform oscillating operation and output amplifiers 102 a-102 j whichbuffer output signals of the delayed differential inverted amplifiers101 a-101 j to output multiphase clock signals. Shown here is a case ofN=10. The output amplifiers 102 a-102 j buffer oscillation signalsoutput from every other delayed differential inverted amplifiers 101a-101 j connected in a ring form and supply them as multiphase clocksignals R1-R10 to the parallel-serial converter.

[0006]FIG. 2 shows voltage waveforms of the multiphase clock signalsR1-R10 output from the voltage-controlled differential ring oscillatoras shown in FIG. 1. In FIG. 2, an abscissa represents time and anordinate represents voltage. When we let “A” stand for a duration inwhich each clock signal is a high level and “B” for a cycle of the clocksignal, a duty of each clock signal is set at D=A/B=0.5.

[0007]FIG. 3A shows wirings or interconnects for three clock signals R1,R2, R3 formed in a semiconductor integrated circuit and capacitors C_(p)equivalently representing stray capacities between these wirings. FIG.3B shows how crosstalks due to stray capacities degrade the voltagewaveforms of the clock signals. As shown in FIG. 3B, a clock signal R2undergoes voltage variations under the influence of crosstalks due tostray capacities each time the adjacent clock signals R1 and R3 changetheir voltage levels. An amount of voltage variation ΔV increases withthe stray capacity C_(p). In clock signals, information at thetransition point is important, and therefore, crosstalk near thetransition point has great effects on precision of the clock signals.

[0008] To generate high-speed and small-amplitude serial signals, it isnecessary to use multiphase clock signals having high frequencies. Theuse of multiphase clock signals having increased frequencies, however,results in that the phase difference to between the multiphase clocksignals as shown in FIG. 3B becomes shorter, which in turn makes atransition waveform of the clock signal R2 more likely to be degraded byvoltage variations due to the crosstalk induced when the adjacent clocksignals R1 and R3 perform voltage level transitions. It is thereforedesired that the circuit for generating high-speed and small-amplitudeserial signals be designed to have as small stray capacities C_(p) aspossible.

[0009] The stray capacities C_(p) can be reduced, for example, byincreasing the distance between the multiphase clock signal wirings asshown in FIG. 4A. FIG. 4A shows an example in which an interval of themultiphase clock signal wirings is increased by two times to halve thestray capacities. This method, however, increases a wiring area for themultiphase clock signals.

[0010] Another technique for reducing the electrostatic coupling betweenadjacent two clock signal wirings may involve arranging another wiringbetween the adjacent two clock signal wirings as shown in FIG. 4B. FIG.4B shows the new wiring added between adjacent two clock signal wiringsand the new wiring is grounded. Alternatively, the new wiring may besupplied with a stable voltage. Such a technique can shield the adjacenttwo clock signal wirings electrostatically from one another and preventpossible degradations of clock signal waveforms which would otherwise becaused by level transitions of the adjacent clock signals. Thistechnique, however, requires an additional area for laying the newwirings, increasing the wiring area for the multiphase clock signals.

[0011] On the other hand, a number of multiphase clock signals havingthe same phase difference tends to increase at an accelerating rate inthe future for a higher-speed serial communication. Hence, arrangingwirings for the multiphase clock signals using the above-mentionedconventional technique requires a large wiring area, giving rise to aproblem of an increased semiconductor substrate area. Under thesecircumstances, there are growing demands for a semiconductor integratedcircuit that can prevent degradation of waveforms of multiphase clocksignals without increasing the wiring area.

DISCLOSURE OF THE INVENTION

[0012] It is therefore an object of the present invention to provide asemiconductor integrated circuit that can prevent multiphase clocksignals having the same phase difference, which signals are generated bya multi-stage differential ring oscillator and transmitted to othercircuits, from being degraded in waveform due to electrostatic couplingbetween wirings thereof and that enables the multiphase clock signals tobe wired in as small an area as possible.

[0013] To achieve the above object, a semiconductor integrated circuitaccording to the present invention comprises: multiple stages ofamplifier circuits, connected in a ring form, for performing oscillatingoperation; a logic circuit for performing logic operation on the basisof predetermined ones of output signals of the multiple stages ofamplifier circuits to output a plurality of clock signals havingdifferent phases from each other and duties not equal to 0.5; and aplurality of wirings for transmitting the plurality of clock signalsoutput from the logic circuit.

[0014] According to the present invention, it is possible to preventdegradations of multiphase clock signal waveforms due to straycapacities without increasing the wiring area of the multiphase clocksignals.

BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Advantages and features of the present invention will becomeapparent when taken in conjunction with the following detaileddescription and the accompanying drawings. In these drawings, the samereference number represents identical constitutional elements.

[0016]FIG. 1 is a circuit diagram showing a configuration of avoltage-controlled differential ring oscillator used in conventionalsemiconductor integrated circuits.

[0017]FIG. 2 is a waveform diagram showing voltage waveforms ofmultiphase clock signals output from the voltage controlled differentialring oscillator as shown in FIG. 1.

[0018]FIG. 3A is a schematic diagram showing multiphase clock signalwirings in a conventional semiconductor integrated circuits andequivalents of stray capacities between these wirings, and FIG. 3B is awaveform diagram showing how the voltage waveform of a clock signal isdegraded by crosstalk due to the stray capacity.

[0019]FIGS. 4A and 4B show wirings in the conventional semiconductorintegrated circuit which are modified to prevent degradations ofwaveforms of the multiphase clock signals.

[0020]FIG. 5 shows a configuration of a semiconductor integrated circuitaccording to a first embodiment of the present invention.

[0021]FIG. 6 is a waveform diagram showing voltage waveforms ofmultiphase clock signals output from a voltage-controlled differentialring oscillator as shown in FIG. 5.

[0022]FIG. 7A shows an example arrangement of wirings in thesemiconductor integrated circuit according to the first embodiment ofthe present invention, and FIG. 7B shows voltage waveforms of clocksignals in the example arrangement of wirings as shown in FIG. 7A.

[0023]FIG. 8A shows an arrangement of multiphase clock signal wirings inthe semiconductor integrated circuit according to the first embodimentof the present invention, and FIG. 8B shows an example arrangement ofmultiphase clock signal wirings in a conventional semiconductorintegrated circuit.

[0024]FIG. 9 is a waveform diagram showing voltage waveforms ofmultiphase clock signals output from a voltage-controlled differentialring oscillator in a semiconductor integrated circuit according to asecond embodiment of the present invention.

[0025]FIG. 10A shows an arrangement of multiphase clock signal wiringsin the semiconductor integrated circuit according to the secondembodiment of the present invention, and FIG. 10B shows voltagewaveforms of the multiphase clock signals in the arrangement as shown inFIG. 10A.

[0026]FIG. 11 is a waveform diagram showing voltage waveforms ofmultiphase clock signals output from a voltage-controlled differentialring oscillator in a semiconductor integrated circuit according to athird embodiment of the present invention.

[0027]FIG. 12A shows an arrangement of multiphase clock signal wiringsin the semiconductor integrated circuit according to the thirdembodiment of the present invention, and FIG. 12B shows voltagewaveforms of the multiphase clock signals in the wiring arrangement asshown in FIG. 12A.

BEST MODE FOR CARRYING OUT THE INVENTION

[0028]FIG. 5 shows a configuration of a semiconductor integrated circuitaccording to a first embodiment of the present invention. As shown inFIG. 5, this semiconductor integrated circuit includes avoltage-controlled differential ring oscillator 500 for outputtingmultiphase clock signals and a parallel-serial converter 600 forconverting received parallel data into serial data on the basis of themultiphase clock signals. The parallel-serial converter 600 may beprovided on the outside of the semiconductor integrated circuit.

[0029] The voltage-controlled differential ring oscillator 500 includesN stages of delayed differential inverted amplifiers 101 a, 101 b, . . .for performing oscillating operation and logic circuits 502 a, 502 b, .. . for performing logic operation on the basis of output signals of thedelayed differential inverted amplifiers 101 a, 101 b, . . . to outputclock signals having M phases. Generally, it is preferred that N is apositive even number and M is an even number within a range from 2 to N.Here, we will take a case of N=M=10 for example.

[0030] Each of the delayed differential inverted amplifiers 101 a-101 jamplifies a difference between a signal applied to a non-inverted inputterminal and a signal applied to an inverted input terminal and suppliesthe amplified differential signal to a non-inverted output terminal andan inverted output terminal. The delayed differential invertedamplifiers 101 a-101 j are connected in a ring form so that anon-inverted output terminal of the previous stage is connected to aninverted input terminal of the subsequent stage and an inverted outputterminal of the previous stage is connected to a non-inverted inputterminal of the subsequent stage. It is noted, however, that anon-inverted output terminal of a delayed differential invertedamplifier 101 j is connected to a non-inverted input terminal of adelayed differential inverted amplifier 101 a and that an invertedoutput terminal of the delayed differential inverted amplifier 101 j isconnected to an inverted input terminal of the delayed differentialinverted amplifier 101 a. With this arrangement, a signal phase isinverted after passing through the ring once. The delay time of each ofthe delayed differential inverted amplifiers 101 a-101 j is controlledby an applied control voltage or control current, allowing theoscillation frequency of the voltage-controlled differential ringoscillator 500 to be adjusted.

[0031] In this embodiment, the logic circuits include M AND gates 502a-502 j. An AND gate 502 a has one input terminal connected to theinverted output terminal of the delayed differential inverted amplifier101 a and the other input terminal connected to the non-inverted outputterminal of the delayed differential inverted amplifier 11 e. One inputterminal of an AND gate 502 b is connected to the inverted outputterminal of the delayed differential inverted amplifier 101 c and theother input terminal is connected to the non-inverted output terminal ofthe delayed differential inverted amplifier 101 g. The subsequent ANDgates 502 c-502 j are connected in the similar manner. Thus, the ANDgates 502 a-502 j produce multiphase clock signals S1-S10 as shown inFIG. 6.

[0032] In FIG. 6, when a duration in which the clock signal is high isdenoted as “A” and a cycle of the clock signal as “B”, then a duty ofthe clock signal D=A/B is expressed as follows:

D=(0.5−2/N)  (1)

[0033] If N=10, equation (1) results in D=0.3<0.5. Hence, two clocksignal wirings can be combined such that one clock signal transits froma low level to a high level or from the high level to the low level whenanother clock signal is maintained at the low level (in this embodiment,ground potential). In this embodiment, sets of combined clock signalwirings (S1, S6), (S2, S7), (S3, S8), (S4, S9), and (S5, S10) are used.

[0034] Among the above sets of clock signal wirings, a set of clocksignal wirings (S1, S6) is shown in FIG. 7A as an example of wiringarrangement. In FIG. 7A, a wiring for a clock signal S1 and a wiring fora clock signal S6 are arranged in parallel on a semiconductor substrate.On the outside of these wirings, ground wirings GND are arranged forelectrostatic shielding. FIG. 7B shows voltage waveforms of the clocksignals S1 and S6 in the wiring arrangement as shown in FIG. 7A.

[0035] As described above, the set of clock signal wirings (S1, S6) isso arranged that one clock signal changes its level when another clocksignal is maintained at a low level (at a ground voltage level). Theclock signal wiring at the ground voltage level has a sufficiently smallimpedance compared with an impedance of a crosstalk source, andtherefore, it has a function of electrostatic shield in the same way asa ground wiring GND. For example, when the clock signal S6 has theground voltage level, a wiring for the clock signal S1 is shielded by aground wiring GND and a wiring for the clock signal S6. Therefore, asshown in FIG. 7B, if the clock signal S1 changes its level in thisperiod, its waveform is protected against being deformed at that time.

[0036] Similarly, as to other sets of clock signal wirings, in a periodwhen one of the two clock signal wirings is at a low level, the other ofthe two clock signal wirings is virtually shielded. Therefore, byarranging clock signal wirings with ground wirings for shielding everyset of clock signal wirings as described above, it is possible toprevent waveform deformations of multiphase clock signals that wouldotherwise be caused by electrostatic coupling between the wirings.

[0037]FIG. 8A shows an arrangement of multiphase clock signal wiringsaccording to this embodiment and, for comparison, FIG. 8B shows anexample of conventional arrangement of multiphase clock signal wirings.In this embodiment as shown in FIG. 8A, the sets of clock signal wirings(S1, S6), (S2, S7), (S3, S8), (S4, S9) and (S5, S10) each has two clocksignal wirings arranged parallel to each other on the semiconductorsubstrate are arranged with ground wirings GND inserted betweenrespective two sets of clock signal wirings. On the other hand, in theconventional arrangement as shown in FIG. 8B, clock signal wiringsR1-R10 and ground wirings GND are alternately arranged on thesemiconductor substrate. Comparison between FIG. 8A and FIG. 8B showsthat the wiring area of the semiconductor substrate in this embodimentis about 25% less than that in the conventional technique.

[0038] Next, a semiconductor integrated circuit according to a secondembodiment of the present invention will be described. The secondembodiment uses the N-stage voltage-controlled differential ringoscillator as shown in FIG. 5 in a condition of N=12.

[0039]FIG. 9 shows voltage waveforms of multiphase clock signals S1-S12output from the 12-stage voltage-controlled differential ringoscillator. In this embodiment, the duty D of each clock signal isobtained from equation (1) as D=0.167. Hence, clock signal wirings aregrouped into plural sets of three clock signal wirings and, in each setof three clock signal wirings, it is possible that when one clock signalchanges its level, both of the other two clock signals are maintained ata low level. For example, in this embodiment, clock signals are groupedinto plural sets of three clock signals by using plural sets of clocksignal wirings (S1, 5, S9), (S2, S6, S10), (S3, S7, S11) and (S4, S8,S12). In each set of clock signal wirings, when one of the three clocksignals changes its level, the other two clock signals can be certainlymaintained at a low level.

[0040]FIG. 10A shows an arrangement of multiphase clock signal wiringsin the semiconductor integrated circuit according to this embodiment. Asshown in FIG. 10A, in each of the sets of clock signal wirings (S1, S5,S9), (S2, S6, S10), (S3, S7, S11) and (S4, S8, S12), three clock signalwirings are arranged parallel to each other on the semiconductorsubstrate, with ground wirings GND interposed between respective twosets of clock signal wirings.

[0041]FIG. 10B shows voltage waveforms of clock signals S1, S5, S9 inthe semiconductor integrated circuit of this embodiment. As shown inFIG. 10B, when the clock signal S5 performs a voltage level transition,the clock signals S1 and S9 are certainly maintained at a low level.Therefore, the wiring for the clock signal S5 is virtually shielded bythe wirings for the clock signals S1 and S9 and no voltage waveformdeformation is observed with the clock signal S5 at that time. Further,when the clock signal S1 or S9 changes its voltage level, the clocksignal S5 is certainly maintained at a low level, so that wiring for theclock signal S1 or S9 is virtually shielded by wiring for the clocksignal S5 and a ground wiring GND.

[0042] As described above, according to this embodiment, the wiring areaof the semiconductor substrate can be reduced by approximately 36%compared with that of the conventional arrangement in which clock signalwirings and ground wirings are alternately arranged.

[0043] Next, a semiconductor integrated circuit according to a thirdembodiment of the present invention will be described. The thirdembodiment uses the N-stage voltage-controlled differential ringoscillator as shown in FIG. 5 in a condition of N=16.

[0044]FIG. 11 shows voltage waveforms of multiphase clock signals S1-S16output from the 16-stage voltage-controlled differential ringoscillator. In this embodiment, the duty D of each clock signal isobtained from equation (1) as D=0.125. Hence, clock signal wirings aregrouped into plural sets of four clock signal wirings and, in each setof four clock signal wirings, it is possible that when one clock signalchanges its level, the remaining three clock signals are maintained at alow level. For example, in this embodiment, clock signals are groupedinto plural sets of four clock signals by using plural sets of fourclock signal wirings (S1, S5, S9, S13), (S2, S6, S10, S14), (S3, S7,S11, S15) and (S4, S8, S12, S16).

[0045]FIG. 12A shows an arrangement of multiphase clock signal wiringsin the semiconductor integrated circuit according to this embodiment. Asshown in FIG. 12A, in each set of clock signal wirings (S1, S5, S9,S13), (S2, S6, S10, S14), (S3, S7, S11, S15) and (S4, S8, S12, S16),four clock signal wirings are arranged parallel to each other on thesemiconductor substrate, with ground wirings GND interposed betweenrespective two sets of clock signal wirings.

[0046]FIG. 12B shows voltage waveforms of clock signals S1, S5, S9, S13in the semiconductor integrated circuit according to this embodiment. Asshown in FIG. 12B, when one of the clock signals in each set performs avoltage level transition, the remaining three clock signals arecertainly maintained at a low level. Therefore, wiring of thelevel-changing clock signal is virtually shielded by wirings of theadjacent clock signal wirings and no voltage waveform deformation isobserved with the level-changing clock signal at that time.

[0047] As described above, according to this embodiment, the wiring areaof the semiconductor substrate can be reduced by approximately 37%compared with that of the conventional arrangement in which clock signalwirings and ground wirings are alternately arranged.

[0048] Although a ground wiring for electrostatic shielding is arrangedbetween respective two set of clock signal wirings as a technique forpreventing degradation of signals due to electrostatic coupling betweenrespective two sets of clock signal wirings in the above embodiments, atechnique for preventing degradation of signals between respective twosets of clock signal wirings is not limited to this arrangement. Thepresent invention can also be realized by employing other techniques. Anexample of such techniques involves increasing a distance betweenrespective two sets of clock signal wirings to reduce stray capacitiesbetween adjacent two sets of clock signal wirings.

[0049] Although the voltage-controlled differential ring oscillator hasbeen employed in the above embodiments, the present invention can beapplied to and implemented by any oscillator as long as it generatesmultiphase clock signals having the same phase difference. Thus, thepresent invention is not limited to the voltage-controlled differentialring oscillator and can be modified within a scope of claims.

[0050] According to the present invention, it is possible to preventdegradations of signal waveforms due to electrostatic coupling betweenmultiphase clock signal wirings while reducing the wiring area of asemiconductor substrate for the multiphase clock signal wirings.

INDUSTRICAL APPLICABILITY

[0051] The present invention can be applied to semiconductor integratedcircuits having a multi-stage ring oscillator that generates multiphaseclock signals having the same phase difference.

1. A semiconductor integrated circuit comprising: multiple stages ofamplifier circuits, connected in a ring form, for performing oscillatingoperation; a logic circuit for performing logic operation on the basisof predetermined ones of output signals of said multiple stages ofamplifier circuits to output a plurality of clock signals havingdifferent phases from each other and duties not equal to 0.5; and aplurality of wirings for transmitting said plurality of clock signalsoutput from said logic circuit.
 2. A semiconductor integrated circuitaccording to claim 1, further comprising a parallel-serial conversioncircuit for converting input parallel data into serial data on the basisof said plurality of clock signals.
 3. A semiconductor integratedcircuit according to claim 1, wherein each of said multiple stages ofamplifier circuits amplifies a difference between a signal applied to anon-inverted input terminal and a signal applied to an inverted inputterminal and supplies a differential signal thus obtained to anon-inverted output terminal and an inverted output terminal.
 4. Asemiconductor integrated circuit according to claim 1, wherein a delaytime of each of said multiple stages of amplifier circuits is controlledby one of a control voltage and a control current.
 5. A semiconductorintegrated circuit according to claim 1, wherein said multiple stages ofamplifier circuits include N stages of differential circuits and saidlogic circuit outputs M clock signals having different phases from eachother, where N is a positive even number and M is an even number withina range from 2 to N.
 6. A semiconductor integrated circuit according toclaim 5, wherein said logic circuit includes M AND gates, each obtaininglogical multiply of two of the output signals of said multiple stages ofamplifier circuits to output one clock signal.
 7. A semiconductorintegrated circuit according to claim 1, wherein a first wiring and asecond wiring are arranged parallel to each other and said first wiringundergoes voltage transition between a first voltage and a secondvoltage when said second wiring has the second voltage.
 8. Asemiconductor integrated circuit according to claim 7, wherein saidsecond voltage is a ground voltage.
 9. A semiconductor integratedcircuit according to claim 1, wherein: a first wiring and at least onewiring together form a set of wirings and said first wiring undergoesvoltage transition between a first voltage and a second voltage whensaid at least one wiring has the second voltage; and a distance betweena wiring included in said set and a wiring not included in said set islarger than a distance between two adjacent wirings included in saidset.
 10. A semiconductor integrated circuit according to claim 9,wherein said second voltage is a ground voltage.
 11. A semiconductorintegrated circuit according to claim 9, wherein another wiring isarranged between said wiring included in said set and said wiring notincluded in said set.
 12. A semiconductor integrated circuit accordingto claim 10, wherein said another wiring is grounded.
 13. Asemiconductor integrated circuit according to claim 1, wherein saidmultiple stages of amplifier circuits include N stages of differentialcircuits and said logic circuit outputs M clock signals having differentphases from each other and duties not larger than (0.5−2/N), where N isa positive even number and M is an even number within a range from 2 toN.
 14. A semiconductor integrated circuit according to claim 13, whereinsaid logic circuit includes M AND gates, each obtaining logical multiplyof two of the output signals of said multiple stages of amplifiercircuits to output one clock signal.
 15. A semiconductor integratedcircuit according to claim 13, wherein a first wiring and a secondwiring are arranged parallel to each other and said first wiringundergoes voltage transition between a first voltage and a secondvoltage when said second wiring has the second voltage.
 16. Asemiconductor integrated circuit according to claim 15, wherein saidsecond voltage is a ground voltage.
 17. A semiconductor integratedcircuit according to claim 13, wherein: a first wiring and at least onewiring together form a set of wirings and said first wiring undergoesvoltage transition between a first voltage and a second voltage whensaid at least one wiring has the second voltage; and a distance betweena wiring included in said set and a wiring not included in said set islarger than a distance between two adjacent wirings included in saidset.
 18. A semiconductor integrated circuit according to claim 17,wherein said second voltage is a ground voltage.
 19. A semiconductorintegrated circuit according to claim 17, wherein another wiring isarranged between said wiring included in said set and said wiring notincluded in said set.
 20. A semiconductor integrated circuit accordingto claim 19, wherein said another wiring is grounded.